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<div class="textblock"><dl class="section note"><dt>Note</dt><dd>None.</dd></dl>
<p>MODIFICATION HISTORY:</p>
<p>Ver Who Date Changes </p>
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<p> 1.00a rpoolla 04/26/13 First release 4.00 vns 09/10/15 Added DFT control bits addresses 7.2 am 07/13/21 Fixed doxygen warnings</p>
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Macros</h2></td></tr>
<tr class="memitem:ae7d9ec0764ee0106216f6a3367a9aa9f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ae7d9ec0764ee0106216f6a3367a9aa9f">XSK_EFUSEPS_RSA_KEY_HASH_LEN_BITS</a>&#160;&#160;&#160;(256)</td></tr>
<tr class="memdesc:ae7d9ec0764ee0106216f6a3367a9aa9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rsa Key hash length in bits.  <a href="#ae7d9ec0764ee0106216f6a3367a9aa9f">More...</a><br/></td></tr>
<tr class="separator:ae7d9ec0764ee0106216f6a3367a9aa9f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0cfd99da0c4f2aa0d72469db347bdfda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a0cfd99da0c4f2aa0d72469db347bdfda">XSK_EFUSEPS_RSA_HASH_LEN_ECC_CALC</a>&#160;&#160;&#160;(260)</td></tr>
<tr class="memdesc:a0cfd99da0c4f2aa0d72469db347bdfda"><td class="mdescLeft">&#160;</td><td class="mdescRight">Rsa Key hash length calculation.  <a href="#a0cfd99da0c4f2aa0d72469db347bdfda">More...</a><br/></td></tr>
<tr class="separator:a0cfd99da0c4f2aa0d72469db347bdfda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28a3e32054644f36176a139ba4fff520"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a28a3e32054644f36176a139ba4fff520">XSK_EFUSEPS_PRGM_STROBE_WIDTH</a>(RefClk)&#160;&#160;&#160;((12 * (RefClk))/1000000)</td></tr>
<tr class="memdesc:a28a3e32054644f36176a139ba4fff520"><td class="mdescLeft">&#160;</td><td class="mdescRight">Strobe width calculation.  <a href="#a28a3e32054644f36176a139ba4fff520">More...</a><br/></td></tr>
<tr class="separator:a28a3e32054644f36176a139ba4fff520"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a576c8c9ba3aa6a1246f498bc9f6ed60c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a576c8c9ba3aa6a1246f498bc9f6ed60c">XSK_EFUSEPS_RD_STROBE_WIDTH</a>(RefClk)&#160;&#160;&#160;((15 * (RefClk))/100000000)</td></tr>
<tr class="memdesc:a576c8c9ba3aa6a1246f498bc9f6ed60c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modified to have max of 32 bit value.  <a href="#a576c8c9ba3aa6a1246f498bc9f6ed60c">More...</a><br/></td></tr>
<tr class="separator:a576c8c9ba3aa6a1246f498bc9f6ed60c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83ebe761588d9b8b10860833cb746a6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a>&#160;&#160;&#160;(0xF800D000)</td></tr>
<tr class="memdesc:a83ebe761588d9b8b10860833cb746a6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PSS eFUSE Register addresses.  <a href="#a83ebe761588d9b8b10860833cb746a6d">More...</a><br/></td></tr>
<tr class="separator:a83ebe761588d9b8b10860833cb746a6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af407b20b4194d9c078658ae97e4823a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#af407b20b4194d9c078658ae97e4823a6">XSK_EFUSEPS_WR_LOCK_REG_OFFSET</a>&#160;&#160;&#160;(0x0)</td></tr>
<tr class="memdesc:af407b20b4194d9c078658ae97e4823a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">WR_LOCK Write lock offset.  <a href="#af407b20b4194d9c078658ae97e4823a6">More...</a><br/></td></tr>
<tr class="separator:af407b20b4194d9c078658ae97e4823a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6974adcd348488808f7aa8fccaeb9533"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a6974adcd348488808f7aa8fccaeb9533">XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET</a>&#160;&#160;&#160;(0x4)</td></tr>
<tr class="memdesc:a6974adcd348488808f7aa8fccaeb9533"><td class="mdescLeft">&#160;</td><td class="mdescRight">WR_UNLOCK Write 0xDF0D to allow write offset.  <a href="#a6974adcd348488808f7aa8fccaeb9533">More...</a><br/></td></tr>
<tr class="separator:a6974adcd348488808f7aa8fccaeb9533"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad97de6a7f673891f7e562e76ec4df13c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ad97de6a7f673891f7e562e76ec4df13c">XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET</a>&#160;&#160;&#160;(0x8)</td></tr>
<tr class="memdesc:ad97de6a7f673891f7e562e76ec4df13c"><td class="mdescLeft">&#160;</td><td class="mdescRight">WR_LOCKSTA Write protection status offset.  <a href="#ad97de6a7f673891f7e562e76ec4df13c">More...</a><br/></td></tr>
<tr class="separator:ad97de6a7f673891f7e562e76ec4df13c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4fe9fbe5a644d7779892e9edc1058791"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a4fe9fbe5a644d7779892e9edc1058791">XSK_EFUSEPS_CONFIG_REG_OFFSET</a>&#160;&#160;&#160;(0xC)</td></tr>
<tr class="memdesc:a4fe9fbe5a644d7779892e9edc1058791"><td class="mdescLeft">&#160;</td><td class="mdescRight">CFG Configuration register offset.  <a href="#a4fe9fbe5a644d7779892e9edc1058791">More...</a><br/></td></tr>
<tr class="separator:a4fe9fbe5a644d7779892e9edc1058791"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a161ad724298fc7d9827bd98c565954fc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a161ad724298fc7d9827bd98c565954fc">XSK_EFUSEPS_STATUS_REG_OFFSET</a>&#160;&#160;&#160;(0x10)</td></tr>
<tr class="memdesc:a161ad724298fc7d9827bd98c565954fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">STATUS Status register offset.  <a href="#a161ad724298fc7d9827bd98c565954fc">More...</a><br/></td></tr>
<tr class="separator:a161ad724298fc7d9827bd98c565954fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85cdd9088f6d91e27e2f07b9a4c20bc1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a85cdd9088f6d91e27e2f07b9a4c20bc1">XSK_EFUSEPS_CONTROL_REG_OFFSET</a>&#160;&#160;&#160;(0x14)</td></tr>
<tr class="memdesc:a85cdd9088f6d91e27e2f07b9a4c20bc1"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONTROL Control register offset.  <a href="#a85cdd9088f6d91e27e2f07b9a4c20bc1">More...</a><br/></td></tr>
<tr class="separator:a85cdd9088f6d91e27e2f07b9a4c20bc1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4e53a41436c197bcd64236ef178da2c8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a4e53a41436c197bcd64236ef178da2c8">XSK_EFUSEPS_PGM_STBW_REG_OFFSET</a>&#160;&#160;&#160;(0x18)</td></tr>
<tr class="memdesc:a4e53a41436c197bcd64236ef178da2c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PGM_STBW eFuse program strobe width register offset.  <a href="#a4e53a41436c197bcd64236ef178da2c8">More...</a><br/></td></tr>
<tr class="separator:a4e53a41436c197bcd64236ef178da2c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd6144e5e4692602259cb57e4db47148"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#afd6144e5e4692602259cb57e4db47148">XSK_EFUSEPS_RD_STBW_REG_OFFSET</a>&#160;&#160;&#160;(0x1C)</td></tr>
<tr class="memdesc:afd6144e5e4692602259cb57e4db47148"><td class="mdescLeft">&#160;</td><td class="mdescRight">RD_STBW eFuse read strobe width register offset.  <a href="#afd6144e5e4692602259cb57e4db47148">More...</a><br/></td></tr>
<tr class="separator:afd6144e5e4692602259cb57e4db47148"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1444e3f0e61dc50eac55f2265d75f208"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a1444e3f0e61dc50eac55f2265d75f208">XSK_EFUSEPS_WR_LOCK_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#af407b20b4194d9c078658ae97e4823a6">XSK_EFUSEPS_WR_LOCK_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a1444e3f0e61dc50eac55f2265d75f208"><td class="mdescLeft">&#160;</td><td class="mdescRight">WR_LOCK Write 0x767B to disallow write.  <a href="#a1444e3f0e61dc50eac55f2265d75f208">More...</a><br/></td></tr>
<tr class="separator:a1444e3f0e61dc50eac55f2265d75f208"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a4932f081f5ec96c124539decda878e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a7a4932f081f5ec96c124539decda878e">XSK_EFUSEPS_WR_UNLOCK_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a6974adcd348488808f7aa8fccaeb9533">XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a7a4932f081f5ec96c124539decda878e"><td class="mdescLeft">&#160;</td><td class="mdescRight">WR_UNLOCK Write 0xDF0D to allow write.  <a href="#a7a4932f081f5ec96c124539decda878e">More...</a><br/></td></tr>
<tr class="separator:a7a4932f081f5ec96c124539decda878e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1875b31b104b6d1fe4c371e450cf2f6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a1875b31b104b6d1fe4c371e450cf2f6d">XSK_EFUSEPS_WR_LOCK_STATUS_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#ad97de6a7f673891f7e562e76ec4df13c">XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a1875b31b104b6d1fe4c371e450cf2f6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">WR_LOCKSTA Write protection status.  <a href="#a1875b31b104b6d1fe4c371e450cf2f6d">More...</a><br/></td></tr>
<tr class="separator:a1875b31b104b6d1fe4c371e450cf2f6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a181241481bae878db9c1b8bc45eebd3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a181241481bae878db9c1b8bc45eebd3d">XSK_EFUSEPS_CONFIG_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a4fe9fbe5a644d7779892e9edc1058791">XSK_EFUSEPS_CONFIG_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a181241481bae878db9c1b8bc45eebd3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CFG Configuration register.  <a href="#a181241481bae878db9c1b8bc45eebd3d">More...</a><br/></td></tr>
<tr class="separator:a181241481bae878db9c1b8bc45eebd3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f4977445c365f71eda60b2bba84727c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a3f4977445c365f71eda60b2bba84727c">XSK_EFUSEPS_STATUS_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a161ad724298fc7d9827bd98c565954fc">XSK_EFUSEPS_STATUS_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a3f4977445c365f71eda60b2bba84727c"><td class="mdescLeft">&#160;</td><td class="mdescRight">STATUS Status register.  <a href="#a3f4977445c365f71eda60b2bba84727c">More...</a><br/></td></tr>
<tr class="separator:a3f4977445c365f71eda60b2bba84727c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a37aa46e53d68f6c77c5e3d6f9a6943aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a37aa46e53d68f6c77c5e3d6f9a6943aa">XSK_EFUSEPS_CONTROL_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a85cdd9088f6d91e27e2f07b9a4c20bc1">XSK_EFUSEPS_CONTROL_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a37aa46e53d68f6c77c5e3d6f9a6943aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONTROL Control register.  <a href="#a37aa46e53d68f6c77c5e3d6f9a6943aa">More...</a><br/></td></tr>
<tr class="separator:a37aa46e53d68f6c77c5e3d6f9a6943aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4d7fe5bd7667d9a57c238328f343d95c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a4d7fe5bd7667d9a57c238328f343d95c">XSK_EFUSEPS_PGM_STBW_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a4e53a41436c197bcd64236ef178da2c8">XSK_EFUSEPS_PGM_STBW_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a4d7fe5bd7667d9a57c238328f343d95c"><td class="mdescLeft">&#160;</td><td class="mdescRight">PGM_STBW eFuse program strobe width register.  <a href="#a4d7fe5bd7667d9a57c238328f343d95c">More...</a><br/></td></tr>
<tr class="separator:a4d7fe5bd7667d9a57c238328f343d95c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9383ce46dbabb7c855569ef88ed73dc6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a9383ce46dbabb7c855569ef88ed73dc6">XSK_EFUSEPS_RD_STBW_REG</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#afd6144e5e4692602259cb57e4db47148">XSK_EFUSEPS_RD_STBW_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:a9383ce46dbabb7c855569ef88ed73dc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">RD_STBW eFuse read strobe width register.  <a href="#a9383ce46dbabb7c855569ef88ed73dc6">More...</a><br/></td></tr>
<tr class="separator:a9383ce46dbabb7c855569ef88ed73dc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a534303385585d8e6e3473ec38290046c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a534303385585d8e6e3473ec38290046c">XSK_EFUSEPS_WR_LOCK_STATUS_BIT</a>&#160;&#160;&#160;(0x1)</td></tr>
<tr class="memdesc:a534303385585d8e6e3473ec38290046c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Current state of write protection mode of eFuse subsystem:- 0 Region is writable 1 Region is not writable.  <a href="#a534303385585d8e6e3473ec38290046c">More...</a><br/></td></tr>
<tr class="separator:a534303385585d8e6e3473ec38290046c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a17f066dac9ba22ce1a91853bc1914318"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a17f066dac9ba22ce1a91853bc1914318">XSK_EFUSEPS_CONFIG_REDUNDANCY</a>&#160;&#160;&#160;(0x00010000)</td></tr>
<tr class="memdesc:a17f066dac9ba22ce1a91853bc1914318"><td class="mdescLeft">&#160;</td><td class="mdescRight">Redundancy mode, if set, else single mode.  <a href="#a17f066dac9ba22ce1a91853bc1914318">More...</a><br/></td></tr>
<tr class="separator:a17f066dac9ba22ce1a91853bc1914318"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad585dc497a89d100b768fd0890aa2101"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ad585dc497a89d100b768fd0890aa2101">XSK_EFUSEPS_CONFIG_TSU_H_A</a>&#160;&#160;&#160;(0x00002000)</td></tr>
<tr class="memdesc:ad585dc497a89d100b768fd0890aa2101"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse read/program setup/hold control between address and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles  <a href="#ad585dc497a89d100b768fd0890aa2101">More...</a><br/></td></tr>
<tr class="separator:ad585dc497a89d100b768fd0890aa2101"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa4e0ee432f3b586a86148c375e8d2dcd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#aa4e0ee432f3b586a86148c375e8d2dcd">XSK_EFUSEPS_CONFIG_TSU_H_CS</a>&#160;&#160;&#160;(0x00001000)</td></tr>
<tr class="memdesc:aa4e0ee432f3b586a86148c375e8d2dcd"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse read/program setup/hold control between csb and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles  <a href="#aa4e0ee432f3b586a86148c375e8d2dcd">More...</a><br/></td></tr>
<tr class="separator:aa4e0ee432f3b586a86148c375e8d2dcd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9bc1c855a43d39990b69664a6b7f1ff0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a9bc1c855a43d39990b69664a6b7f1ff0">XSK_EFUSEPS_CONFIG_TSU_H_PS</a>&#160;&#160;&#160;(0x00000F00)</td></tr>
<tr class="memdesc:a9bc1c855a43d39990b69664a6b7f1ff0"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse program setup/hold control between ps and csb active  <a href="#a9bc1c855a43d39990b69664a6b7f1ff0">More...</a><br/></td></tr>
<tr class="separator:a9bc1c855a43d39990b69664a6b7f1ff0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50b408cab08160fa621794fef3ee3213"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a50b408cab08160fa621794fef3ee3213">XSK_EFUSEPS_CONFIG_CLK_DIV</a>&#160;&#160;&#160;(0x00000003)</td></tr>
<tr class="memdesc:a50b408cab08160fa621794fef3ee3213"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reference clock scaler 2 b00 bypass clock divider 2 b01 div 2 2 b10 div 4 2 h11 div 8.  <a href="#a50b408cab08160fa621794fef3ee3213">More...</a><br/></td></tr>
<tr class="separator:a50b408cab08160fa621794fef3ee3213"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a638c4b3b837b5923feae3c3f8eaf2455"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a638c4b3b837b5923feae3c3f8eaf2455">XSK_EFUSEPS_STATUS_BISR_DONE</a>&#160;&#160;&#160;(0x80000000)</td></tr>
<tr class="memdesc:a638c4b3b837b5923feae3c3f8eaf2455"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register containing BISR Controller status, trim value, and security debug info.  <a href="#a638c4b3b837b5923feae3c3f8eaf2455">More...</a><br/></td></tr>
<tr class="separator:a638c4b3b837b5923feae3c3f8eaf2455"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a42ef35e2f36887032a5d0774cdb437eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a42ef35e2f36887032a5d0774cdb437eb">XSK_EFUSEPS_STATUS_BISR_GO</a>&#160;&#160;&#160;(0x40000000)</td></tr>
<tr class="memdesc:a42ef35e2f36887032a5d0774cdb437eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Build in self test finished successfully.  <a href="#a42ef35e2f36887032a5d0774cdb437eb">More...</a><br/></td></tr>
<tr class="separator:a42ef35e2f36887032a5d0774cdb437eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a22b344d6d93a34f5e40ae50e03995cd6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a22b344d6d93a34f5e40ae50e03995cd6">XSK_EFUSEPS_STATUS_BISR_BLANK</a>&#160;&#160;&#160;(0x00100000)</td></tr>
<tr class="memdesc:a22b344d6d93a34f5e40ae50e03995cd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse box is blank, i.e., not yet been written to, if set  <a href="#a22b344d6d93a34f5e40ae50e03995cd6">More...</a><br/></td></tr>
<tr class="separator:a22b344d6d93a34f5e40ae50e03995cd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8f5f42bfc559c3378a54c4a0be3be1f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a8f5f42bfc559c3378a54c4a0be3be1f5">XSK_EFUSEPS_STATUS_SDEBUG_DIS</a>&#160;&#160;&#160;(0x00010000)</td></tr>
<tr class="memdesc:a8f5f42bfc559c3378a54c4a0be3be1f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Security debug status, with authentication 0 security debug enabled 1 security debug disabled.  <a href="#a8f5f42bfc559c3378a54c4a0be3be1f5">More...</a><br/></td></tr>
<tr class="separator:a8f5f42bfc559c3378a54c4a0be3be1f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aff176dab0e87749acd3503b47f785293"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#aff176dab0e87749acd3503b47f785293">XSK_EFUSEPS_STATUS_WR_PROTECT</a>&#160;&#160;&#160;(0x00003000)</td></tr>
<tr class="memdesc:aff176dab0e87749acd3503b47f785293"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse write protection, if either bit is set, writes to the eFuse box are disabled  <a href="#aff176dab0e87749acd3503b47f785293">More...</a><br/></td></tr>
<tr class="separator:aff176dab0e87749acd3503b47f785293"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a062fc27f143cc35cfda61ab224c1c622"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a062fc27f143cc35cfda61ab224c1c622">XSK_EFUSEPS_STATUS_TRIM</a>&#160;&#160;&#160;(0x000000FC)</td></tr>
<tr class="memdesc:a062fc27f143cc35cfda61ab224c1c622"><td class="mdescLeft">&#160;</td><td class="mdescRight">Analog trim value.  <a href="#a062fc27f143cc35cfda61ab224c1c622">More...</a><br/></td></tr>
<tr class="separator:a062fc27f143cc35cfda61ab224c1c622"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c34f551c39236943d36103cb150353b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a1c34f551c39236943d36103cb150353b">XSK_EFUSEPS_CONTROL_PS_EN</a>&#160;&#160;&#160;(0x00000010)</td></tr>
<tr class="memdesc:a1c34f551c39236943d36103cb150353b"><td class="mdescLeft">&#160;</td><td class="mdescRight">XSK_EFUSEPS_CONTROL_REG (Control register for eFuse program, read and write control) eFuse ps control, enable programming if set.  <a href="#a1c34f551c39236943d36103cb150353b">More...</a><br/></td></tr>
<tr class="separator:a1c34f551c39236943d36103cb150353b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9c6d0eb879aee49e3109cba85d60a5ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a9c6d0eb879aee49e3109cba85d60a5ff">XSK_EFUSEPS_CONTROL_WR_DIS</a>&#160;&#160;&#160;(0x00000002)</td></tr>
<tr class="memdesc:a9c6d0eb879aee49e3109cba85d60a5ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse write disable, if set.  <a href="#a9c6d0eb879aee49e3109cba85d60a5ff">More...</a><br/></td></tr>
<tr class="separator:a9c6d0eb879aee49e3109cba85d60a5ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a634af4b7edb7109523e14d841c4ac283"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a634af4b7edb7109523e14d841c4ac283">XSK_EFUSEPS_CONTROL_RD_DIS</a>&#160;&#160;&#160;(0x00000001)</td></tr>
<tr class="memdesc:a634af4b7edb7109523e14d841c4ac283"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse read disable, if set  <a href="#a634af4b7edb7109523e14d841c4ac283">More...</a><br/></td></tr>
<tr class="separator:a634af4b7edb7109523e14d841c4ac283"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a165e873a3967c54e34bfbb53e08a6616"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a165e873a3967c54e34bfbb53e08a6616">XSK_EFUSEPS_APB_START_ADDR_OFFSET</a>&#160;&#160;&#160;(0x1000)</td></tr>
<tr class="memdesc:a165e873a3967c54e34bfbb53e08a6616"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key start address offset  <a href="#a165e873a3967c54e34bfbb53e08a6616">More...</a><br/></td></tr>
<tr class="separator:a165e873a3967c54e34bfbb53e08a6616"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abfe6334a050009ee6898e9a8c8685ab7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#abfe6334a050009ee6898e9a8c8685ab7">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET</a>&#160;&#160;&#160;(0x20)</td></tr>
<tr class="memdesc:abfe6334a050009ee6898e9a8c8685ab7"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key first half start address offset  <a href="#abfe6334a050009ee6898e9a8c8685ab7">More...</a><br/></td></tr>
<tr class="separator:abfe6334a050009ee6898e9a8c8685ab7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae29504e97df93bc4d7accc1492b18c25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ae29504e97df93bc4d7accc1492b18c25">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET</a>&#160;&#160;&#160;(0x24)</td></tr>
<tr class="memdesc:ae29504e97df93bc4d7accc1492b18c25"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key second half start address offset  <a href="#ae29504e97df93bc4d7accc1492b18c25">More...</a><br/></td></tr>
<tr class="separator:ae29504e97df93bc4d7accc1492b18c25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add6f0b527dda840825debf7f21c402dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#add6f0b527dda840825debf7f21c402dc">XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET</a>&#160;&#160;&#160;(0x28)</td></tr>
<tr class="memdesc:add6f0b527dda840825debf7f21c402dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for ROM 128k CRC enable offset  <a href="#add6f0b527dda840825debf7f21c402dc">More...</a><br/></td></tr>
<tr class="separator:add6f0b527dda840825debf7f21c402dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0887192e1bd9d2d8b6af5e0a2ed8c724"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a0887192e1bd9d2d8b6af5e0a2ed8c724">XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET</a>&#160;&#160;&#160;(0x2C)</td></tr>
<tr class="memdesc:a0887192e1bd9d2d8b6af5e0a2ed8c724"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for RSA authentication enable offset  <a href="#a0887192e1bd9d2d8b6af5e0a2ed8c724">More...</a><br/></td></tr>
<tr class="separator:a0887192e1bd9d2d8b6af5e0a2ed8c724"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0c13de15173d8f4f6d3ab38f7aae1571"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a0c13de15173d8f4f6d3ab38f7aae1571">XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET</a>&#160;&#160;&#160;(0x30)</td></tr>
<tr class="memdesc:a0c13de15173d8f4f6d3ab38f7aae1571"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE DFT JTAG disable  <a href="#a0c13de15173d8f4f6d3ab38f7aae1571">More...</a><br/></td></tr>
<tr class="separator:a0c13de15173d8f4f6d3ab38f7aae1571"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a65bd389db45d8c5c293bcd5d2ae67786"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a65bd389db45d8c5c293bcd5d2ae67786">XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET</a>&#160;&#160;&#160;(0x34)</td></tr>
<tr class="memdesc:a65bd389db45d8c5c293bcd5d2ae67786"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE DFT mode disable  <a href="#a65bd389db45d8c5c293bcd5d2ae67786">More...</a><br/></td></tr>
<tr class="separator:a65bd389db45d8c5c293bcd5d2ae67786"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a049f16d265f4a8cdcf7e1a11b468dbe9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a049f16d265f4a8cdcf7e1a11b468dbe9">XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET</a>&#160;&#160;&#160;(0x5C0)</td></tr>
<tr class="memdesc:a049f16d265f4a8cdcf7e1a11b468dbe9"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for RSA uart status enable on MIO48 offset  <a href="#a049f16d265f4a8cdcf7e1a11b468dbe9">More...</a><br/></td></tr>
<tr class="separator:a049f16d265f4a8cdcf7e1a11b468dbe9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5877ed2d9cc5938045fb722931b8c2a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#af5877ed2d9cc5938045fb722931b8c2a">XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET</a>&#160;&#160;&#160;(0x5C4)</td></tr>
<tr class="memdesc:af5877ed2d9cc5938045fb722931b8c2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for non-secure INIT_B signaling offset  <a href="#af5877ed2d9cc5938045fb722931b8c2a">More...</a><br/></td></tr>
<tr class="separator:af5877ed2d9cc5938045fb722931b8c2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1a93a56d790cc46674efbfcf09eaa4ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a1a93a56d790cc46674efbfcf09eaa4ce">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET</a>&#160;&#160;&#160;(0x80)</td></tr>
<tr class="memdesc:a1a93a56d790cc46674efbfcf09eaa4ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled)  <a href="#a1a93a56d790cc46674efbfcf09eaa4ce">More...</a><br/></td></tr>
<tr class="separator:a1a93a56d790cc46674efbfcf09eaa4ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aecff4bb8c83a5a98c59275d77d6a3122"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#aecff4bb8c83a5a98c59275d77d6a3122">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET</a>&#160;&#160;&#160;(0x580)</td></tr>
<tr class="memdesc:aecff4bb8c83a5a98c59275d77d6a3122"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key first half end address  <a href="#aecff4bb8c83a5a98c59275d77d6a3122">More...</a><br/></td></tr>
<tr class="separator:aecff4bb8c83a5a98c59275d77d6a3122"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7443ab3ad3feb2fe33d09df60f580ab3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a7443ab3ad3feb2fe33d09df60f580ab3">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET</a>&#160;&#160;&#160;(0x880)</td></tr>
<tr class="memdesc:a7443ab3ad3feb2fe33d09df60f580ab3"><td class="mdescLeft">&#160;</td><td class="mdescRight">If Single mode is enabled both First and Second half addresses are valid.  <a href="#a7443ab3ad3feb2fe33d09df60f580ab3">More...</a><br/></td></tr>
<tr class="separator:a7443ab3ad3feb2fe33d09df60f580ab3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae52417a54b3a5ccfbb9479117d133378"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ae52417a54b3a5ccfbb9479117d133378">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET</a>&#160;&#160;&#160;(0xE00)</td></tr>
<tr class="memdesc:ae52417a54b3a5ccfbb9479117d133378"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key second half end address  <a href="#ae52417a54b3a5ccfbb9479117d133378">More...</a><br/></td></tr>
<tr class="separator:ae52417a54b3a5ccfbb9479117d133378"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e165a68ae10abe2fe9dace19b70e273"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a8e165a68ae10abe2fe9dace19b70e273">XSK_EFUSEPS_APB_MIRROR_ADDRESS</a>(Addr)&#160;&#160;&#160;(Addr + 0x87C - (2*(Addr%128)))</td></tr>
<tr class="memdesc:a8e165a68ae10abe2fe9dace19b70e273"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mirror Address = addr + 2nd half start address + mirror offset.  <a href="#a8e165a68ae10abe2fe9dace19b70e273">More...</a><br/></td></tr>
<tr class="separator:a8e165a68ae10abe2fe9dace19b70e273"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ada0b9881bc445d6c249bc59600a095f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a165e873a3967c54e34bfbb53e08a6616">XSK_EFUSEPS_APB_START_ADDR_OFFSET</a>)</td></tr>
<tr class="memdesc:ada0b9881bc445d6c249bc59600a095f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB start address  <a href="#ada0b9881bc445d6c249bc59600a095f8">More...</a><br/></td></tr>
<tr class="separator:ada0b9881bc445d6c249bc59600a095f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0248a7f53d9204f32b9de14b855b5d3d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a0248a7f53d9204f32b9de14b855b5d3d">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#abfe6334a050009ee6898e9a8c8685ab7">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET</a>)</td></tr>
<tr class="memdesc:a0248a7f53d9204f32b9de14b855b5d3d"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key second half start address  <a href="#a0248a7f53d9204f32b9de14b855b5d3d">More...</a><br/></td></tr>
<tr class="separator:a0248a7f53d9204f32b9de14b855b5d3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a439afda37a15708eaef5b5e643553d2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a439afda37a15708eaef5b5e643553d2b">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#ae29504e97df93bc4d7accc1492b18c25">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET</a>)</td></tr>
<tr class="memdesc:a439afda37a15708eaef5b5e643553d2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key second half start address  <a href="#a439afda37a15708eaef5b5e643553d2b">More...</a><br/></td></tr>
<tr class="separator:a439afda37a15708eaef5b5e643553d2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a043fd44c43605e5b4992086603099367"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a043fd44c43605e5b4992086603099367">XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#add6f0b527dda840825debf7f21c402dc">XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET</a>)</td></tr>
<tr class="memdesc:a043fd44c43605e5b4992086603099367"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for ROM 128k CRC enable  <a href="#a043fd44c43605e5b4992086603099367">More...</a><br/></td></tr>
<tr class="separator:a043fd44c43605e5b4992086603099367"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab1e2ac0d16c9642260c14232003ade75"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ab1e2ac0d16c9642260c14232003ade75">XSK_EFUSEPS_APB_RSA_AUTH_ENABLE</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a0887192e1bd9d2d8b6af5e0a2ed8c724">XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET</a>)</td></tr>
<tr class="memdesc:ab1e2ac0d16c9642260c14232003ade75"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for RSA authentication enable  <a href="#ab1e2ac0d16c9642260c14232003ade75">More...</a><br/></td></tr>
<tr class="separator:ab1e2ac0d16c9642260c14232003ade75"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab3e22310d214573799dd3337599f5dde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ab3e22310d214573799dd3337599f5dde">XSK_EFUSEPS_APB_DFT_JTAG_DISABLE</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a0c13de15173d8f4f6d3ab38f7aae1571">XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET</a>)</td></tr>
<tr class="memdesc:ab3e22310d214573799dd3337599f5dde"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse DFT JTAG disable  <a href="#ab3e22310d214573799dd3337599f5dde">More...</a><br/></td></tr>
<tr class="separator:ab3e22310d214573799dd3337599f5dde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa9c2a75e70d7dd0ac999bb7b2157dbec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#aa9c2a75e70d7dd0ac999bb7b2157dbec">XSK_EFUSEPS_APB_DFT_MODE_DISABLE</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a65bd389db45d8c5c293bcd5d2ae67786">XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET</a>)</td></tr>
<tr class="memdesc:aa9c2a75e70d7dd0ac999bb7b2157dbec"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse DFT mode disable  <a href="#aa9c2a75e70d7dd0ac999bb7b2157dbec">More...</a><br/></td></tr>
<tr class="separator:aa9c2a75e70d7dd0ac999bb7b2157dbec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ace877925292c5fbb88a28c7c1bf1279e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ace877925292c5fbb88a28c7c1bf1279e">XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a049f16d265f4a8cdcf7e1a11b468dbe9">XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET</a>)</td></tr>
<tr class="memdesc:ace877925292c5fbb88a28c7c1bf1279e"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for RSA uart status enable on MIO48  <a href="#ace877925292c5fbb88a28c7c1bf1279e">More...</a><br/></td></tr>
<tr class="separator:ace877925292c5fbb88a28c7c1bf1279e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acbb32ce4ae6a1d3059f0ec5c5cfea9f3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#acbb32ce4ae6a1d3059f0ec5c5cfea9f3">XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#af5877ed2d9cc5938045fb722931b8c2a">XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET</a>)</td></tr>
<tr class="memdesc:acbb32ce4ae6a1d3059f0ec5c5cfea9f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE APB address for non-secure INIT_B signaling  <a href="#acbb32ce4ae6a1d3059f0ec5c5cfea9f3">More...</a><br/></td></tr>
<tr class="separator:acbb32ce4ae6a1d3059f0ec5c5cfea9f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a68a62676abd39b736317a3bca368d197"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a68a62676abd39b736317a3bca368d197">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a1a93a56d790cc46674efbfcf09eaa4ce">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET</a>)</td></tr>
<tr class="memdesc:a68a62676abd39b736317a3bca368d197"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled)  <a href="#a68a62676abd39b736317a3bca368d197">More...</a><br/></td></tr>
<tr class="separator:a68a62676abd39b736317a3bca368d197"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a29c6023f9017125c4956fc512e7c1fc5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a29c6023f9017125c4956fc512e7c1fc5">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#aecff4bb8c83a5a98c59275d77d6a3122">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET</a>)</td></tr>
<tr class="memdesc:a29c6023f9017125c4956fc512e7c1fc5"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key first half end address  <a href="#a29c6023f9017125c4956fc512e7c1fc5">More...</a><br/></td></tr>
<tr class="separator:a29c6023f9017125c4956fc512e7c1fc5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5fb5012989538614ca570c433360b329"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a5fb5012989538614ca570c433360b329">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a7443ab3ad3feb2fe33d09df60f580ab3">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET</a>)</td></tr>
<tr class="memdesc:a5fb5012989538614ca570c433360b329"><td class="mdescLeft">&#160;</td><td class="mdescRight">If Single mode is enabled both First and Second half addresses are valid.  <a href="#a5fb5012989538614ca570c433360b329">More...</a><br/></td></tr>
<tr class="separator:a5fb5012989538614ca570c433360b329"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a689716b14355b57079d4bded7a39b62f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a689716b14355b57079d4bded7a39b62f">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#ae52417a54b3a5ccfbb9479117d133378">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET</a>)</td></tr>
<tr class="memdesc:a689716b14355b57079d4bded7a39b62f"><td class="mdescLeft">&#160;</td><td class="mdescRight">eFuse memory APB Customer key second half end address  <a href="#a689716b14355b57079d4bded7a39b62f">More...</a><br/></td></tr>
<tr class="separator:a689716b14355b57079d4bded7a39b62f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e165a68ae10abe2fe9dace19b70e273"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a8e165a68ae10abe2fe9dace19b70e273">XSK_EFUSEPS_APB_MIRROR_ADDRESS</a>(Addr)&#160;&#160;&#160;(Addr + 0x87C - (2*(Addr%128)))</td></tr>
<tr class="memdesc:a8e165a68ae10abe2fe9dace19b70e273"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mirror Address = addr + 2nd half start address + mirror offset.  <a href="#a8e165a68ae10abe2fe9dace19b70e273">More...</a><br/></td></tr>
<tr class="separator:a8e165a68ae10abe2fe9dace19b70e273"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a440b422d4faa0d2d13a4c4fb59ae0bb1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a440b422d4faa0d2d13a4c4fb59ae0bb1">XSK_EFUSEPS_CONTROLER_LOCK</a>()&#160;&#160;&#160;Xil_Out32(<a class="el" href="xilskey__epshw_8h.html#a1444e3f0e61dc50eac55f2265d75f208">XSK_EFUSEPS_WR_LOCK_REG</a>,0x767B)</td></tr>
<tr class="memdesc:a440b422d4faa0d2d13a4c4fb59ae0bb1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro is used to lock the efuse controller.  <a href="#a440b422d4faa0d2d13a4c4fb59ae0bb1">More...</a><br/></td></tr>
<tr class="separator:a440b422d4faa0d2d13a4c4fb59ae0bb1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a14cfddcfbb88c1b0c7c8c0559b22896c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a14cfddcfbb88c1b0c7c8c0559b22896c">XSK_EFUSEPS_CONTROLER_UNLOCK</a>()&#160;&#160;&#160;Xil_Out32(<a class="el" href="xilskey__epshw_8h.html#a7a4932f081f5ec96c124539decda878e">XSK_EFUSEPS_WR_UNLOCK_REG</a>,0xDF0D)</td></tr>
<tr class="memdesc:a14cfddcfbb88c1b0c7c8c0559b22896c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro is used to unlock the efuse controller.  <a href="#a14cfddcfbb88c1b0c7c8c0559b22896c">More...</a><br/></td></tr>
<tr class="separator:a14cfddcfbb88c1b0c7c8c0559b22896c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0d28dedee1ceb722c49cb6da990a3199"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a0d28dedee1ceb722c49cb6da990a3199">XSK_EFUSEPS_CONTROLER_LOCK_STATUS</a>()&#160;&#160;&#160;(Xil_In32(<a class="el" href="xilskey__epshw_8h.html#a1875b31b104b6d1fe4c371e450cf2f6d">XSK_EFUSEPS_WR_LOCK_STATUS_REG</a>) &amp; 0x1)</td></tr>
<tr class="memdesc:a0d28dedee1ceb722c49cb6da990a3199"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro is used to check the status whether eFuse controller is locked or not.  <a href="#a0d28dedee1ceb722c49cb6da990a3199">More...</a><br/></td></tr>
<tr class="separator:a0d28dedee1ceb722c49cb6da990a3199"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeaaa9012301edfc03993c1e5e7cec9d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#aeaaa9012301edfc03993c1e5e7cec9d3">XSK_EFUSEPS_CONTROLER_OP_MODE</a>()&#160;&#160;&#160;((Xil_In32(<a class="el" href="xilskey__epshw_8h.html#a181241481bae878db9c1b8bc45eebd3d">XSK_EFUSEPS_CONFIG_REG</a>) &amp; <a class="el" href="xilskey__epshw_8h.html#a17f066dac9ba22ce1a91853bc1914318">XSK_EFUSEPS_CONFIG_REDUNDANCY</a>)? 1 : 0)</td></tr>
<tr class="memdesc:aeaaa9012301edfc03993c1e5e7cec9d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro is used to determine operation mode of efuse controller.  <a href="#aeaaa9012301edfc03993c1e5e7cec9d3">More...</a><br/></td></tr>
<tr class="separator:aeaaa9012301edfc03993c1e5e7cec9d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab40242d2cc93420c7a7bb744ddfee68c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ab40242d2cc93420c7a7bb744ddfee68c">XilSKey_EfusePs_IsEfuseWriteProtected</a>()&#160;&#160;&#160;((Xil_In32(<a class="el" href="xilskey__epshw_8h.html#a3f4977445c365f71eda60b2bba84727c">XSK_EFUSEPS_STATUS_REG</a>) &amp; <a class="el" href="xilskey__epshw_8h.html#aff176dab0e87749acd3503b47f785293">XSK_EFUSEPS_STATUS_WR_PROTECT</a>)? TRUE : FALSE)</td></tr>
<tr class="memdesc:ab40242d2cc93420c7a7bb744ddfee68c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro is used to check whether eFuse is write protected or not.  <a href="#ab40242d2cc93420c7a7bb744ddfee68c">More...</a><br/></td></tr>
<tr class="separator:ab40242d2cc93420c7a7bb744ddfee68c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Hamming information</div></td></tr>
<tr class="memitem:ad98b11e83cb73a07a9db478d61855bbc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ad98b11e83cb73a07a9db478d61855bbc">XSK_EFUSEPS_HAMMING_LOOPS</a>&#160;&#160;&#160;(10)</td></tr>
<tr class="memdesc:ad98b11e83cb73a07a9db478d61855bbc"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Hamming loops, data and length  <a href="#ad98b11e83cb73a07a9db478d61855bbc">More...</a><br/></td></tr>
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<tr class="memitem:a969b5f8374b830f57d01329b1dc2ad41"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a969b5f8374b830f57d01329b1dc2ad41"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_HAMMING_LENGTH</b>&#160;&#160;&#160;(31)</td></tr>
<tr class="separator:a969b5f8374b830f57d01329b1dc2ad41"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a649f05b0ab3ff80e390859cf70511cd2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a649f05b0ab3ff80e390859cf70511cd2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_HAMMING_DATA</b>&#160;&#160;&#160;(26)</td></tr>
<tr class="separator:a649f05b0ab3ff80e390859cf70511cd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Mode types</div></td></tr>
<tr class="memitem:ab89168a190f2b176fc52aa119fbfd4bb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ab89168a190f2b176fc52aa119fbfd4bb">XSK_EFUSEPS_SINGLE_MODE</a>&#160;&#160;&#160;(0x0)</td></tr>
<tr class="memdesc:ab89168a190f2b176fc52aa119fbfd4bb"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Mode types and definitions  <a href="#ab89168a190f2b176fc52aa119fbfd4bb">More...</a><br/></td></tr>
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<tr class="memitem:adc54f9b43642ddc8fb0a881ac8909786"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adc54f9b43642ddc8fb0a881ac8909786"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_REDUNDANCY_MODE</b>&#160;&#160;&#160;(0x1)</td></tr>
<tr class="separator:adc54f9b43642ddc8fb0a881ac8909786"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">ReadMode</div></td></tr>
<tr class="memitem:afd1d475c7976c8d4057f1f422b38caa0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#afd1d475c7976c8d4057f1f422b38caa0">XSK_EFUSEPS_READ_MODE_NORMAL</a>&#160;&#160;&#160;(0x1)</td></tr>
<tr class="memdesc:afd1d475c7976c8d4057f1f422b38caa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; ReadModes and definitions  <a href="#afd1d475c7976c8d4057f1f422b38caa0">More...</a><br/></td></tr>
<tr class="separator:afd1d475c7976c8d4057f1f422b38caa0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af9c8b0aa6a104685eeb3fae492ab24d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af9c8b0aa6a104685eeb3fae492ab24d2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_READ_MODE_MARGIN_1</b>&#160;&#160;&#160;(0x2)</td></tr>
<tr class="separator:af9c8b0aa6a104685eeb3fae492ab24d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1ee78bd2b127c6ad0029b8ffb94cf4d3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1ee78bd2b127c6ad0029b8ffb94cf4d3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_READ_MODE_MARGIN_2</b>&#160;&#160;&#160;(0x3)</td></tr>
<tr class="separator:a1ee78bd2b127c6ad0029b8ffb94cf4d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">EFUSE operation modes</div></td></tr>
<tr class="memitem:a8b6db89bcacd73a511cfc74cd117d058"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a8b6db89bcacd73a511cfc74cd117d058">XSK_EFUSEPS_ENABLE_PROGRAMMING</a>&#160;&#160;&#160;(0x1)</td></tr>
<tr class="memdesc:a8b6db89bcacd73a511cfc74cd117d058"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; EFUSE operation modes and definitions  <a href="#a8b6db89bcacd73a511cfc74cd117d058">More...</a><br/></td></tr>
<tr class="separator:a8b6db89bcacd73a511cfc74cd117d058"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2d6b89b111a2c77db49db84cd0fd7fd2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2d6b89b111a2c77db49db84cd0fd7fd2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_ENABLE_READ</b>&#160;&#160;&#160;(0x2)</td></tr>
<tr class="separator:a2d6b89b111a2c77db49db84cd0fd7fd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac41c16b0c5663cd9b6a65cb9679fc352"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac41c16b0c5663cd9b6a65cb9679fc352"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_ENABLE_WRITE</b>&#160;&#160;&#160;(0x4)</td></tr>
<tr class="separator:ac41c16b0c5663cd9b6a65cb9679fc352"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">EFUSE Reference Clock frequency</div></td></tr>
<tr class="memitem:a1926299738dd5272aaddea96259bffb0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a1926299738dd5272aaddea96259bffb0">XSK_EFUSEPS_REFCLK_LOW_FREQ</a>&#160;&#160;&#160;(20000000)</td></tr>
<tr class="memdesc:a1926299738dd5272aaddea96259bffb0"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; EFUSE Reference Clock frequency definitions  <a href="#a1926299738dd5272aaddea96259bffb0">More...</a><br/></td></tr>
<tr class="separator:a1926299738dd5272aaddea96259bffb0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0fee4be52a89e5d2656d57855f36f642"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0fee4be52a89e5d2656d57855f36f642"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_REFCLK_HIGH_FREQ</b>&#160;&#160;&#160;(60000000)</td></tr>
<tr class="separator:a0fee4be52a89e5d2656d57855f36f642"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">eFuse read margin control</div></td></tr>
<tr class="memitem:a44765f342f2b29344ce3c4c272e76e73"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a44765f342f2b29344ce3c4c272e76e73">XSK_EFUSEPS_CONFIG_MARGIN_RD</a>&#160;&#160;&#160;(0x00000030)</td></tr>
<tr class="memdesc:a44765f342f2b29344ce3c4c272e76e73"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; eFuse read margin control: 00 normal, 01 margin 1, 10 margin 2, 11 - undefined  <a href="#a44765f342f2b29344ce3c4c272e76e73">More...</a><br/></td></tr>
<tr class="separator:a44765f342f2b29344ce3c4c272e76e73"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a886ee77d622f5e4f3b00003b1d232e07"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a886ee77d622f5e4f3b00003b1d232e07"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_CONFIG_RD_NORMAL</b>&#160;&#160;&#160;(0x00000000)</td></tr>
<tr class="separator:a886ee77d622f5e4f3b00003b1d232e07"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a567e7773b55d03fa7a3cd649f4f2d3a1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a567e7773b55d03fa7a3cd649f4f2d3a1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_CONFIG_RD_MARGIN_1</b>&#160;&#160;&#160;(0x00000010)</td></tr>
<tr class="separator:a567e7773b55d03fa7a3cd649f4f2d3a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee5df238a10e2d88e1be379ffe1cb31d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aee5df238a10e2d88e1be379ffe1cb31d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_CONFIG_RD_MARGIN_2</b>&#160;&#160;&#160;(0x00000020)</td></tr>
<tr class="separator:aee5df238a10e2d88e1be379ffe1cb31d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Xilinx reserved Tests bits registers</div></td></tr>
<tr class="memitem:a09ac3e69110fb08bc3dab9c7b11fa057"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a09ac3e69110fb08bc3dab9c7b11fa057">XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET</a>&#160;&#160;&#160;(0x80)</td></tr>
<tr class="memdesc:a09ac3e69110fb08bc3dab9c7b11fa057"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Xilinx reserved Tests bits in the First half of the eFUSE block offsets and definitions  <a href="#a09ac3e69110fb08bc3dab9c7b11fa057">More...</a><br/></td></tr>
<tr class="separator:a09ac3e69110fb08bc3dab9c7b11fa057"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aecf1e4b1986fc609edaa154917bb5d4b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aecf1e4b1986fc609edaa154917bb5d4b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41_OFFSET</b>&#160;&#160;&#160;(0x104)</td></tr>
<tr class="separator:aecf1e4b1986fc609edaa154917bb5d4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7dd44cd7ebeb9049206e06ad24262575"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7dd44cd7ebeb9049206e06ad24262575"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62_OFFSET</b>&#160;&#160;&#160;(0x188)</td></tr>
<tr class="separator:a7dd44cd7ebeb9049206e06ad24262575"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4e7dfbd3f351aea27a21bc8c39e3b279"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4e7dfbd3f351aea27a21bc8c39e3b279"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83_OFFSET</b>&#160;&#160;&#160;(0x20C)</td></tr>
<tr class="separator:a4e7dfbd3f351aea27a21bc8c39e3b279"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6f2087e52d0f813053d89daf1b0e6ba0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6f2087e52d0f813053d89daf1b0e6ba0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4_OFFSET</b>&#160;&#160;&#160;(0x290)</td></tr>
<tr class="separator:a6f2087e52d0f813053d89daf1b0e6ba0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aefe441d552b4dc5561e15d01ad119aa9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aefe441d552b4dc5561e15d01ad119aa9"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5_OFFSET</b>&#160;&#160;&#160;(0x314)</td></tr>
<tr class="separator:aefe441d552b4dc5561e15d01ad119aa9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a05696f0f8f3f72be6e42acd074291895"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a05696f0f8f3f72be6e42acd074291895"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6_OFFSET</b>&#160;&#160;&#160;(0x398)</td></tr>
<tr class="separator:a05696f0f8f3f72be6e42acd074291895"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa5b52b6cbab03cf370643228aa4c066a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa5b52b6cbab03cf370643228aa4c066a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107_OFFSET</b>&#160;&#160;&#160;(0x41C)</td></tr>
<tr class="separator:aa5b52b6cbab03cf370643228aa4c066a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a32fc9214663b7718ce89e0602bc7b30d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a32fc9214663b7718ce89e0602bc7b30d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128_OFFSET</b>&#160;&#160;&#160;(0x4A0)</td></tr>
<tr class="separator:a32fc9214663b7718ce89e0602bc7b30d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5f168c866b6ea2b893896d322eab4abf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5f168c866b6ea2b893896d322eab4abf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149_OFFSET</b>&#160;&#160;&#160;(0x524)</td></tr>
<tr class="separator:a5f168c866b6ea2b893896d322eab4abf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92042b886fa4d085f97667799bedfc57"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a92042b886fa4d085f97667799bedfc57"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET</b>&#160;&#160;&#160;(0x8FC)</td></tr>
<tr class="separator:a92042b886fa4d085f97667799bedfc57"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaa3ef88fe7dc395e0e964f220a247ea6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaa3ef88fe7dc395e0e964f220a247ea6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E_OFFSET</b>&#160;&#160;&#160;(0x978)</td></tr>
<tr class="separator:aaa3ef88fe7dc395e0e964f220a247ea6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac27e95aae6c68bcdcd6731ef43dac271"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac27e95aae6c68bcdcd6731ef43dac271"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D_OFFSET</b>&#160;&#160;&#160;(0x9F4)</td></tr>
<tr class="separator:ac27e95aae6c68bcdcd6731ef43dac271"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9174d98587fcdd733d15c364af2a0a5d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9174d98587fcdd733d15c364af2a0a5d"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C_OFFSET</b>&#160;&#160;&#160;(0xA70)</td></tr>
<tr class="separator:a9174d98587fcdd733d15c364af2a0a5d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aea43549f9ae5bec4414f3e9496a04988"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aea43549f9ae5bec4414f3e9496a04988"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB_OFFSET</b>&#160;&#160;&#160;(0xAEC)</td></tr>
<tr class="separator:aea43549f9ae5bec4414f3e9496a04988"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7a80a7ce0f27cbdc4db380a61a1245e6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7a80a7ce0f27cbdc4db380a61a1245e6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA_OFFSET</b>&#160;&#160;&#160;(0xB68)</td></tr>
<tr class="separator:a7a80a7ce0f27cbdc4db380a61a1245e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7ff5460c1b41ae0d6df77eefbe7d0883"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7ff5460c1b41ae0d6df77eefbe7d0883"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9_OFFSET</b>&#160;&#160;&#160;(0xBE4)</td></tr>
<tr class="separator:a7ff5460c1b41ae0d6df77eefbe7d0883"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5fd621e9add2d0a9dbae7a4739aeaaf8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5fd621e9add2d0a9dbae7a4739aeaaf8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318_OFFSET</b>&#160;&#160;&#160;(0xC60)</td></tr>
<tr class="separator:a5fd621e9add2d0a9dbae7a4739aeaaf8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb40e5cb79cb23a13f9a6ec5e6b2820b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abb40e5cb79cb23a13f9a6ec5e6b2820b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337_OFFSET</b>&#160;&#160;&#160;(0xCDC)</td></tr>
<tr class="separator:abb40e5cb79cb23a13f9a6ec5e6b2820b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a208ec3d3d57ba00a1073d9a6d6b20ff3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a208ec3d3d57ba00a1073d9a6d6b20ff3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356_OFFSET</b>&#160;&#160;&#160;(0xD58)</td></tr>
<tr class="separator:a208ec3d3d57ba00a1073d9a6d6b20ff3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a41ab2c70aedfae0e4d2c8b26f773926f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a41ab2c70aedfae0e4d2c8b26f773926f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_OFFSET</b>&#160;&#160;&#160;(0x1C)</td></tr>
<tr class="separator:a41ab2c70aedfae0e4d2c8b26f773926f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d243739137b673302fa41c7b318cd3e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6d243739137b673302fa41c7b318cd3e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_OFFSET</b>&#160;&#160;&#160;(0x40)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_OFFSET</b>&#160;&#160;&#160;(0x7C)</td></tr>
<tr class="separator:ac6138da192d83a026ebc53a1b5d4a09c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50c15e9804d3405327e95e7b305efb9a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a50c15e9804d3405327e95e7b305efb9a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_OFFSET</b>&#160;&#160;&#160;(0x600)</td></tr>
<tr class="separator:a50c15e9804d3405327e95e7b305efb9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7dbc38f5b3545459cd9a10540fc6c60e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7dbc38f5b3545459cd9a10540fc6c60e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_OFFSET</b>&#160;&#160;&#160;(0x7FC)</td></tr>
<tr class="separator:a7dbc38f5b3545459cd9a10540fc6c60e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aab9e805d693bfc91f1d0a51596129a27"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#aab9e805d693bfc91f1d0a51596129a27">XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET</a>&#160;&#160;&#160;(0x860)</td></tr>
<tr class="memdesc:aab9e805d693bfc91f1d0a51596129a27"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Xilinx reserved Tests bits in the Second half of the eFUSE block offsets  <a href="#aab9e805d693bfc91f1d0a51596129a27">More...</a><br/></td></tr>
<tr class="separator:aab9e805d693bfc91f1d0a51596129a27"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF_OFFSET</b>&#160;&#160;&#160;(0x87C)</td></tr>
<tr class="separator:a69c0cb7085ccd88a828f3ea988cabfef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa62a39086e4e826f1af7247a4e1c422e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa62a39086e4e826f1af7247a4e1c422e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF_OFFSET</b>&#160;&#160;&#160;(0x800)</td></tr>
<tr class="separator:aa62a39086e4e826f1af7247a4e1c422e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0db220f3ebe5c2842426829f531192b7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0db220f3ebe5c2842426829f531192b7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF_OFFSET</b>&#160;&#160;&#160;(0x83C)</td></tr>
<tr class="separator:a0db220f3ebe5c2842426829f531192b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae3c6bd72823c418d7d0a7ee8ac261dff"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae3c6bd72823c418d7d0a7ee8ac261dff"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF_OFFSET</b>&#160;&#160;&#160;(0xE00)</td></tr>
<tr class="separator:ae3c6bd72823c418d7d0a7ee8ac261dff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a773913189f4e98f0e437c2190fc5b83a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a773913189f4e98f0e437c2190fc5b83a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF_OFFSET</b>&#160;&#160;&#160;(0xFFC)</td></tr>
<tr class="separator:a773913189f4e98f0e437c2190fc5b83a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a81347f7506085d433d18c529b7f8d6e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a81347f7506085d433d18c529b7f8d6e6">XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a09ac3e69110fb08bc3dab9c7b11fa057">XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET</a>)</td></tr>
<tr class="memdesc:a81347f7506085d433d18c529b7f8d6e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Xilinx reserved Tests bits in the First half of the eFUSE block address  <a href="#a81347f7506085d433d18c529b7f8d6e6">More...</a><br/></td></tr>
<tr class="separator:a81347f7506085d433d18c529b7f8d6e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50b33cd1e1953e724d1a58311570f5a3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a50b33cd1e1953e724d1a58311570f5a3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x41_OFFSET)</td></tr>
<tr class="separator:a50b33cd1e1953e724d1a58311570f5a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6f687d12b943da2e9e9824400685f52c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6f687d12b943da2e9e9824400685f52c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x62_OFFSET)</td></tr>
<tr class="separator:a6f687d12b943da2e9e9824400685f52c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad1984cb80d9968f6bc52b4101e786990"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad1984cb80d9968f6bc52b4101e786990"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x83_OFFSET)</td></tr>
<tr class="separator:ad1984cb80d9968f6bc52b4101e786990"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3c5b9fc6a5191a14101bfc3cd47e2fe4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3c5b9fc6a5191a14101bfc3cd47e2fe4"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xA4_OFFSET)</td></tr>
<tr class="separator:a3c5b9fc6a5191a14101bfc3cd47e2fe4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8013eca5ad237fb99b945932d0ea3313"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8013eca5ad237fb99b945932d0ea3313"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xC5_OFFSET)</td></tr>
<tr class="separator:a8013eca5ad237fb99b945932d0ea3313"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_xE6_OFFSET)</td></tr>
<tr class="separator:a8dbf100d50b1fb8dc24020188afdcb22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5d29f40197dddbd06ac7277c3e79a7c6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5d29f40197dddbd06ac7277c3e79a7c6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x107_OFFSET)</td></tr>
<tr class="separator:a5d29f40197dddbd06ac7277c3e79a7c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aed60e36fcbb48be7cad3427c731062a2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aed60e36fcbb48be7cad3427c731062a2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x128_OFFSET)</td></tr>
<tr class="separator:aed60e36fcbb48be7cad3427c731062a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd9892c60f5ee390ef387c9b310c06db"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afd9892c60f5ee390ef387c9b310c06db"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x149_OFFSET)</td></tr>
<tr class="separator:afd9892c60f5ee390ef387c9b310c06db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a30a30145d45855d1976ec41ef8d3a664"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a30a30145d45855d1976ec41ef8d3a664">XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET)</td></tr>
<tr class="memdesc:a30a30145d45855d1976ec41ef8d3a664"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Xilinx reserved Tests bits in the First half of the eFUSE block address  <a href="#a30a30145d45855d1976ec41ef8d3a664">More...</a><br/></td></tr>
<tr class="separator:a30a30145d45855d1976ec41ef8d3a664"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x25E_OFFSET)</td></tr>
<tr class="separator:acb68d3cc28ea4b76e9dda7511e101dbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6a0bf897ad6e49e937706eac5d6cb9a1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6a0bf897ad6e49e937706eac5d6cb9a1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x27D_OFFSET)</td></tr>
<tr class="separator:a6a0bf897ad6e49e937706eac5d6cb9a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abc9c4bd628d7730c95803426d16a89a2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abc9c4bd628d7730c95803426d16a89a2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x29C_OFFSET)</td></tr>
<tr class="separator:abc9c4bd628d7730c95803426d16a89a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aecfa90060947e8f84b6b2280831080f3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aecfa90060947e8f84b6b2280831080f3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2BB_OFFSET)</td></tr>
<tr class="separator:aecfa90060947e8f84b6b2280831080f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9f7a52a7481302e6842e46565f0268a7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9f7a52a7481302e6842e46565f0268a7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2DA_OFFSET)</td></tr>
<tr class="separator:a9f7a52a7481302e6842e46565f0268a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae84e5aa1588b2707767346fbef243dc0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae84e5aa1588b2707767346fbef243dc0"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x2F9_OFFSET)</td></tr>
<tr class="separator:ae84e5aa1588b2707767346fbef243dc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2b233db5ee7034e1cc7ef06aa4b756d6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2b233db5ee7034e1cc7ef06aa4b756d6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x318_OFFSET)</td></tr>
<tr class="separator:a2b233db5ee7034e1cc7ef06aa4b756d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa41e3aa0e49f2e788f45f4180123cc7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa41e3aa0e49f2e788f45f4180123cc7c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x337_OFFSET)</td></tr>
<tr class="separator:aa41e3aa0e49f2e788f45f4180123cc7c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73ef2e5f073537479d2a0d533e8ff233"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a73ef2e5f073537479d2a0d533e8ff233"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x356_OFFSET)</td></tr>
<tr class="separator:a73ef2e5f073537479d2a0d533e8ff233"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad902de733258e3dee29cba902a315d40"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ad902de733258e3dee29cba902a315d40">XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a>)</td></tr>
<tr class="memdesc:ad902de733258e3dee29cba902a315d40"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Xilinx reserved Tests bits in the First half of the eFUSE block address  <a href="#ad902de733258e3dee29cba902a315d40">More...</a><br/></td></tr>
<tr class="separator:ad902de733258e3dee29cba902a315d40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3df4860ea7ac4a0de5191896f11565b2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3df4860ea7ac4a0de5191896f11565b2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_OFFSET)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_OFFSET)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_OFFSET)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_START_ADDR</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_OFFSET)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_END_ADDR</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_OFFSET)</td></tr>
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<tr class="memitem:ac226f4af9d59902bb9415a7f38992090"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#ac226f4af9d59902bb9415a7f38992090">XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF</a>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#aab9e805d693bfc91f1d0a51596129a27">XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET</a>)</td></tr>
<tr class="memdesc:ac226f4af9d59902bb9415a7f38992090"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; Xilinx reserved Tests bits in the Second half of the eFUSE block address  <a href="#ac226f4af9d59902bb9415a7f38992090">More...</a><br/></td></tr>
<tr class="separator:ac226f4af9d59902bb9415a7f38992090"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_TRIM_BITS_END_ADDR_2ND_HALF_OFFSET)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_START_ADDR_2ND_HALF_OFFSET)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_BITS_END_ADDR_2ND_HALF_OFFSET)</td></tr>
<tr class="separator:adc14383d2256b26b0d9284f77217fcbe"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_BISR_BITS_START_ADDR_2ND_HALF_OFFSET)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF</b>&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_BISR_BITS_END_ADDR_2ND_HALF_OFFSET)</td></tr>
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</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:a8de972831fdeea3f25a593ea7986899a"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a8de972831fdeea3f25a593ea7986899a">XilSKey_EfusePs_GenerateMatrixMap</a> (void)</td></tr>
<tr class="memdesc:a8de972831fdeea3f25a593ea7986899a"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to generate the matrix map of the G and H for hamming code (31,26).  <a href="#a8de972831fdeea3f25a593ea7986899a">More...</a><br/></td></tr>
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<tr class="memitem:a0018fa32b6f940720182140986d422c6"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a0018fa32b6f940720182140986d422c6">XilSKey_EfusePs_EccDecode</a> (const u8 *Corrupt, u8 *Syndrome)</td></tr>
<tr class="memdesc:a0018fa32b6f940720182140986d422c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to decode the incoming encoded byte.  <a href="#a0018fa32b6f940720182140986d422c6">More...</a><br/></td></tr>
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<tr class="memitem:adf842c0bf8f3e7c5d5dcfc8e46f8cf77"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#adf842c0bf8f3e7c5d5dcfc8e46f8cf77">XilSKey_EfusePs_EccEncode</a> (const u8 *InData, u8 *Ecc)</td></tr>
<tr class="memdesc:adf842c0bf8f3e7c5d5dcfc8e46f8cf77"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to encode the incoming data byte.  <a href="#adf842c0bf8f3e7c5d5dcfc8e46f8cf77">More...</a><br/></td></tr>
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<tr class="memitem:a86aa3b42b03a38e86ae622b0338523cc"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig</a> (u8 CtrlMode, u32 RefClk, u8 ReadMode)</td></tr>
<tr class="memdesc:a86aa3b42b03a38e86ae622b0338523cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to set the controller mode, read mode along with the read and program strobe width values based on the reference clock.  <a href="#a86aa3b42b03a38e86ae622b0338523cc">More...</a><br/></td></tr>
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<tr class="memitem:aa96506a89bc84dd4db81ce860cd63ef0"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#aa96506a89bc84dd4db81ce860cd63ef0">XilSKey_EfusePs_IsAddressXilRestricted</a> (u32 Addr)</td></tr>
<tr class="memdesc:aa96506a89bc84dd4db81ce860cd63ef0"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to check whether eFuse bit is xilinx reserved bit or not.  <a href="#aa96506a89bc84dd4db81ce860cd63ef0">More...</a><br/></td></tr>
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<tr class="memitem:a445869d8f60f01261334c1022c4b08f5"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a445869d8f60f01261334c1022c4b08f5">XilSKey_EfusePs_ControllerSetReadWriteEnable</a> (u32 ReadWriteEnable)</td></tr>
<tr class="memdesc:a445869d8f60f01261334c1022c4b08f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to enable the read/write/program the eFUSE array.  <a href="#a445869d8f60f01261334c1022c4b08f5">More...</a><br/></td></tr>
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<tr class="memitem:a35d72d812bd2eedfe0fe1cf855819774"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a35d72d812bd2eedfe0fe1cf855819774">XilSKey_EfusePs_ReadEfuseBit</a> (u32 Addr, u8 *Data)</td></tr>
<tr class="memdesc:a35d72d812bd2eedfe0fe1cf855819774"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to read the eFuse bit value.  <a href="#a35d72d812bd2eedfe0fe1cf855819774">More...</a><br/></td></tr>
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<tr class="memitem:a2c6ad78fcde90b22766572624ce2f236"><td class="memItemLeft" align="right" valign="top">u32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xilskey__epshw_8h.html#a2c6ad78fcde90b22766572624ce2f236">XilSKey_EfusePs_WriteEfuseBit</a> (u32 Addr)</td></tr>
<tr class="memdesc:a2c6ad78fcde90b22766572624ce2f236"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function is used to program the eFuse bit value.  <a href="#a2c6ad78fcde90b22766572624ce2f236">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="ab40242d2cc93420c7a7bb744ddfee68c"></a>
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          <td class="memname">#define XilSKey_EfusePs_IsEfuseWriteProtected</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;((Xil_In32(<a class="el" href="xilskey__epshw_8h.html#a3f4977445c365f71eda60b2bba84727c">XSK_EFUSEPS_STATUS_REG</a>) &amp; <a class="el" href="xilskey__epshw_8h.html#aff176dab0e87749acd3503b47f785293">XSK_EFUSEPS_STATUS_WR_PROTECT</a>)? TRUE : FALSE)</td>
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<p>This macro is used to check whether eFuse is write protected or not. </p>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if eFuse is write protected.</li>
</ul>
</dd></dl>
<ul>
<li>FALSE is eFuse is not write protected. </li>
</ul>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#aecff4bb8c83a5a98c59275d77d6a3122">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET</a>)</td>
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<p>eFuse memory APB Customer key first half end address </p>

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<a class="anchor" id="aecff4bb8c83a5a98c59275d77d6a3122"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_END_ADDR_OFFSET&#160;&#160;&#160;(0x580)</td>
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<p>eFuse memory APB Customer key first half end address </p>

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</div>
<a class="anchor" id="a68a62676abd39b736317a3bca368d197"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a1a93a56d790cc46674efbfcf09eaa4ce">XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET</a>)</td>
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<p>eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled) </p>
<p>If Redundant mode is enabled only First half addresses are valid.</p>
<p>eFuse memory APB Customer key first half start address </p>

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</div>
<a class="anchor" id="a1a93a56d790cc46674efbfcf09eaa4ce"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_FIRST_HALF_START_ADDR_OFFSET&#160;&#160;&#160;(0x80)</td>
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<p>eFUSE bits from 0 to 0x1F and 0x180 to 0x1FF in the First half, and bits from 0x200 to 0x21F and 0x380 to 0x3FF in the Second half(if Single mode is enabled) </p>
<p>If Redundant mode is enabled only First half addresses are valid. eFuse memory APB Customer key first half start address </p>

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<a class="anchor" id="a689716b14355b57079d4bded7a39b62f"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#ae52417a54b3a5ccfbb9479117d133378">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET</a>)</td>
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<p>eFuse memory APB Customer key second half end address </p>

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<a class="anchor" id="ae52417a54b3a5ccfbb9479117d133378"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_END_ADDR_OFFSET&#160;&#160;&#160;(0xE00)</td>
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<p>eFuse memory APB Customer key second half end address </p>

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<a class="anchor" id="a5fb5012989538614ca570c433360b329"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a7443ab3ad3feb2fe33d09df60f580ab3">XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET</a>)</td>
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<p>If Single mode is enabled both First and Second half addresses are valid. </p>
<p>eFuse memory APB Customer key second half start address </p>

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<a class="anchor" id="a7443ab3ad3feb2fe33d09df60f580ab3"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_CUSTOMER_KEY_SECND_HALF_START_ADDR_OFFSET&#160;&#160;&#160;(0x880)</td>
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<p>If Single mode is enabled both First and Second half addresses are valid. </p>
<p>eFuse memory APB Customer key second half start address </p>

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<a class="anchor" id="ab3e22310d214573799dd3337599f5dde"></a>
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          <td class="memname">#define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a0c13de15173d8f4f6d3ab38f7aae1571">XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET</a>)</td>
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<p>eFuse DFT JTAG disable </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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</div>
<a class="anchor" id="a0c13de15173d8f4f6d3ab38f7aae1571"></a>
<div class="memitem">
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          <td class="memname">#define XSK_EFUSEPS_APB_DFT_JTAG_DISABLE_OFFSET&#160;&#160;&#160;(0x30)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFUSE DFT JTAG disable </p>

</div>
</div>
<a class="anchor" id="aa9c2a75e70d7dd0ac999bb7b2157dbec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_DFT_MODE_DISABLE&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a65bd389db45d8c5c293bcd5d2ae67786">XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET</a>)</td>
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      </table>
</div><div class="memdoc">

<p>eFuse DFT mode disable </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

</div>
</div>
<a class="anchor" id="a65bd389db45d8c5c293bcd5d2ae67786"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_DFT_MODE_DISABLE_OFFSET&#160;&#160;&#160;(0x34)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFUSE DFT mode disable </p>

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<a class="anchor" id="a8e165a68ae10abe2fe9dace19b70e273"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSK_EFUSEPS_APB_MIRROR_ADDRESS</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Addr</td><td>)</td>
          <td>&#160;&#160;&#160;(Addr + 0x87C - (2*(Addr%128)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Mirror Address = addr + 2nd half start address + mirror offset. </p>

</div>
</div>
<a class="anchor" id="a8e165a68ae10abe2fe9dace19b70e273"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_MIRROR_ADDRESS</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Addr</td><td>)</td>
          <td>&#160;&#160;&#160;(Addr + 0x87C - (2*(Addr%128)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Mirror Address = addr + 2nd half start address + mirror offset. </p>

</div>
</div>
<a class="anchor" id="a043fd44c43605e5b4992086603099367"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#add6f0b527dda840825debf7f21c402dc">XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET</a>)</td>
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      </table>
</div><div class="memdoc">

<p>eFUSE APB address for ROM 128k CRC enable </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

</div>
</div>
<a class="anchor" id="add6f0b527dda840825debf7f21c402dc"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_ROM_128K_CRC_ENABLE_OFFSET&#160;&#160;&#160;(0x28)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFUSE APB address for ROM 128k CRC enable offset </p>

</div>
</div>
<a class="anchor" id="acbb32ce4ae6a1d3059f0ec5c5cfea9f3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#af5877ed2d9cc5938045fb722931b8c2a">XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFUSE APB address for non-secure INIT_B signaling </p>

</div>
</div>
<a class="anchor" id="af5877ed2d9cc5938045fb722931b8c2a"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_ROM_NONSECURE_INITB_ENABLE_OFFSET&#160;&#160;&#160;(0x5C4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFUSE APB address for non-secure INIT_B signaling offset </p>

</div>
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<a class="anchor" id="ace877925292c5fbb88a28c7c1bf1279e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a049f16d265f4a8cdcf7e1a11b468dbe9">XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET</a>)</td>
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      </table>
</div><div class="memdoc">

<p>eFUSE APB address for RSA uart status enable on MIO48 </p>

</div>
</div>
<a class="anchor" id="a049f16d265f4a8cdcf7e1a11b468dbe9"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_ROM_UART_STATUS_ENABLE_OFFSET&#160;&#160;&#160;(0x5C0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFUSE APB address for RSA uart status enable on MIO48 offset </p>

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<a class="anchor" id="ab1e2ac0d16c9642260c14232003ade75"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a0887192e1bd9d2d8b6af5e0a2ed8c724">XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET</a>)</td>
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      </table>
</div><div class="memdoc">

<p>eFUSE APB address for RSA authentication enable </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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</div>
<a class="anchor" id="a0887192e1bd9d2d8b6af5e0a2ed8c724"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_RSA_AUTH_ENABLE_OFFSET&#160;&#160;&#160;(0x2C)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFUSE APB address for RSA authentication enable offset </p>

</div>
</div>
<a class="anchor" id="ada0b9881bc445d6c249bc59600a095f8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_START_ADDR&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a165e873a3967c54e34bfbb53e08a6616">XSK_EFUSEPS_APB_START_ADDR_OFFSET</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse memory APB start address </p>

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</div>
<a class="anchor" id="a165e873a3967c54e34bfbb53e08a6616"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_START_ADDR_OFFSET&#160;&#160;&#160;(0x1000)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse memory APB Customer key start address offset </p>

</div>
</div>
<a class="anchor" id="ad902de733258e3dee29cba902a315d40"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; Xilinx reserved Tests bits in the First half of the eFUSE block address </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#aa96506a89bc84dd4db81ce860cd63ef0">XilSKey_EfusePs_IsAddressXilRestricted()</a>.</p>

</div>
</div>
<a class="anchor" id="ac226f4af9d59902bb9415a7f38992090"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#aab9e805d693bfc91f1d0a51596129a27">XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; Xilinx reserved Tests bits in the Second half of the eFUSE block address </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#aa96506a89bc84dd4db81ce860cd63ef0">XilSKey_EfusePs_IsAddressXilRestricted()</a>.</p>

</div>
</div>
<a class="anchor" id="aab9e805d693bfc91f1d0a51596129a27"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF_OFFSET&#160;&#160;&#160;(0x860)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; Xilinx reserved Tests bits in the Second half of the eFUSE block offsets </p>

</div>
</div>
<a class="anchor" id="a0248a7f53d9204f32b9de14b855b5d3d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#abfe6334a050009ee6898e9a8c8685ab7">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET</a>)</td>
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      </table>
</div><div class="memdoc">

<p>eFuse memory APB Customer key second half start address </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

</div>
</div>
<a class="anchor" id="abfe6334a050009ee6898e9a8c8685ab7"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_1_OFFSET&#160;&#160;&#160;(0x20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse memory APB Customer key first half start address offset </p>

</div>
</div>
<a class="anchor" id="a439afda37a15708eaef5b5e643553d2b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#ae29504e97df93bc4d7accc1492b18c25">XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse memory APB Customer key second half start address </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

</div>
</div>
<a class="anchor" id="ae29504e97df93bc4d7accc1492b18c25"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_WRITE_PROTECTION_ADDR_2_OFFSET&#160;&#160;&#160;(0x24)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse memory APB Customer key second half start address offset </p>

</div>
</div>
<a class="anchor" id="a81347f7506085d433d18c529b7f8d6e6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + <a class="el" href="xilskey__epshw_8h.html#a09ac3e69110fb08bc3dab9c7b11fa057">XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET</a>)</td>
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<p>&lt; Xilinx reserved Tests bits in the First half of the eFUSE block address </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#aa96506a89bc84dd4db81ce860cd63ef0">XilSKey_EfusePs_IsAddressXilRestricted()</a>.</p>

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</div>
<a class="anchor" id="a09ac3e69110fb08bc3dab9c7b11fa057"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20_OFFSET&#160;&#160;&#160;(0x80)</td>
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      </table>
</div><div class="memdoc">

<p>&lt; Xilinx reserved Tests bits in the First half of the eFUSE block offsets and definitions </p>

</div>
</div>
<a class="anchor" id="a30a30145d45855d1976ec41ef8d3a664"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#ada0b9881bc445d6c249bc59600a095f8">XSK_EFUSEPS_APB_START_ADDR</a> + XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F_OFFSET)</td>
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      </table>
</div><div class="memdoc">

<p>&lt; Xilinx reserved Tests bits in the First half of the eFUSE block address </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#aa96506a89bc84dd4db81ce860cd63ef0">XilSKey_EfusePs_IsAddressXilRestricted()</a>.</p>

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</div>
<a class="anchor" id="a83ebe761588d9b8b10860833cb746a6d"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_BASE_ADDRESS&#160;&#160;&#160;(0xF800D000)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PSS eFUSE Register addresses. </p>
<p>eFuse base address </p>

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<a class="anchor" id="a50b408cab08160fa621794fef3ee3213"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSK_EFUSEPS_CONFIG_CLK_DIV&#160;&#160;&#160;(0x00000003)</td>
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      </table>
</div><div class="memdoc">

<p>Reference clock scaler 2 b00 bypass clock divider 2 b01 div 2 2 b10 div 4 2 h11 div 8. </p>
<p>XSK_EFUSEPS_STATUS_REG (Status Register) </p>

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<a class="anchor" id="a44765f342f2b29344ce3c4c272e76e73"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_CONFIG_MARGIN_RD&#160;&#160;&#160;(0x00000030)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>&lt; eFuse read margin control: 00 normal, 01 margin 1, 10 margin 2, 11 - undefined </p>

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<a class="anchor" id="a17f066dac9ba22ce1a91853bc1914318"></a>
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<div class="memproto">
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          <td class="memname">#define XSK_EFUSEPS_CONFIG_REDUNDANCY&#160;&#160;&#160;(0x00010000)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Redundancy mode, if set, else single mode. </p>
<p>This bit only applies to APB access. BISR and eFuse reader always work in redundancy mode. </p>

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</div>
<a class="anchor" id="a181241481bae878db9c1b8bc45eebd3d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XSK_EFUSEPS_CONFIG_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a4fe9fbe5a644d7779892e9edc1058791">XSK_EFUSEPS_CONFIG_REG_OFFSET</a>)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>CFG Configuration register. </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>.</p>

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</div>
<a class="anchor" id="a4fe9fbe5a644d7779892e9edc1058791"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_CONFIG_REG_OFFSET&#160;&#160;&#160;(0xC)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>CFG Configuration register offset. </p>

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<a class="anchor" id="ad585dc497a89d100b768fd0890aa2101"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XSK_EFUSEPS_CONFIG_TSU_H_A&#160;&#160;&#160;(0x00002000)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse read/program setup/hold control between address and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>.</p>

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</div>
<a class="anchor" id="aa4e0ee432f3b586a86148c375e8d2dcd"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_CONFIG_TSU_H_CS&#160;&#160;&#160;(0x00001000)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse read/program setup/hold control between csb and strobe assert 1 b0 1 ref clock cycle 1 b1 2 ref clock cycles </p>

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</div>
<a class="anchor" id="a9bc1c855a43d39990b69664a6b7f1ff0"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XSK_EFUSEPS_CONFIG_TSU_H_PS&#160;&#160;&#160;(0x00000F00)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>eFuse program setup/hold control between ps and csb active </p>

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<a class="anchor" id="a1c34f551c39236943d36103cb150353b"></a>
<div class="memitem">
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          <td class="memname">#define XSK_EFUSEPS_CONTROL_PS_EN&#160;&#160;&#160;(0x00000010)</td>
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<p>XSK_EFUSEPS_CONTROL_REG (Control register for eFuse program, read and write control) eFuse ps control, enable programming if set. </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a445869d8f60f01261334c1022c4b08f5">XilSKey_EfusePs_ControllerSetReadWriteEnable()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_CONTROL_RD_DIS&#160;&#160;&#160;(0x00000001)</td>
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<p>eFuse read disable, if set </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a445869d8f60f01261334c1022c4b08f5">XilSKey_EfusePs_ControllerSetReadWriteEnable()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_CONTROL_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a85cdd9088f6d91e27e2f07b9a4c20bc1">XSK_EFUSEPS_CONTROL_REG_OFFSET</a>)</td>
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<p>CONTROL Control register. </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a445869d8f60f01261334c1022c4b08f5">XilSKey_EfusePs_ControllerSetReadWriteEnable()</a>.</p>

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<a class="anchor" id="a85cdd9088f6d91e27e2f07b9a4c20bc1"></a>
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          <td class="memname">#define XSK_EFUSEPS_CONTROL_REG_OFFSET&#160;&#160;&#160;(0x14)</td>
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<p>CONTROL Control register offset. </p>

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          <td class="memname">#define XSK_EFUSEPS_CONTROL_WR_DIS&#160;&#160;&#160;(0x00000002)</td>
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<p>eFuse write disable, if set. </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a445869d8f60f01261334c1022c4b08f5">XilSKey_EfusePs_ControllerSetReadWriteEnable()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_CONTROLER_LOCK</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;Xil_Out32(<a class="el" href="xilskey__epshw_8h.html#a1444e3f0e61dc50eac55f2265d75f208">XSK_EFUSEPS_WR_LOCK_REG</a>,0x767B)</td>
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<p>This macro is used to lock the efuse controller. </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#gaf4b1541decb6c6f85a71e95c6023e601">XilSKey_EfusePs_Read()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_CONTROLER_LOCK_STATUS</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;(Xil_In32(<a class="el" href="xilskey__epshw_8h.html#a1875b31b104b6d1fe4c371e450cf2f6d">XSK_EFUSEPS_WR_LOCK_STATUS_REG</a>) &amp; 0x1)</td>
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<p>This macro is used to check the status whether eFuse controller is locked or not. </p>
<dl class="section return"><dt>Returns</dt><dd>- TRUE if the 32 bit Value read from the specified input address<ul>
<li>FALSE if the 32 bit Value not read from the specified input address </li>
</ul>
</dd></dl>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#gaf4b1541decb6c6f85a71e95c6023e601">XilSKey_EfusePs_Read()</a>, <a class="el" href="group__xilskey__zynq__efuse.html#gae3fb5ac72380a5efddd99df27fde3c41">XilSKey_EfusePs_ReadStatus()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_CONTROLER_OP_MODE</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;((Xil_In32(<a class="el" href="xilskey__epshw_8h.html#a181241481bae878db9c1b8bc45eebd3d">XSK_EFUSEPS_CONFIG_REG</a>) &amp; <a class="el" href="xilskey__epshw_8h.html#a17f066dac9ba22ce1a91853bc1914318">XSK_EFUSEPS_CONFIG_REDUNDANCY</a>)? 1 : 0)</td>
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<p>This macro is used to determine operation mode of efuse controller. </p>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>TRUE if eFuse controller mode is redundancy</li>
</ul>
</dd></dl>
<ul>
<li>FALSE if eFuse controller mode is single </li>
</ul>

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          <td class="memname">#define XSK_EFUSEPS_CONTROLER_UNLOCK</td>
          <td>(</td>
          <td class="paramname"></td><td>)</td>
          <td>&#160;&#160;&#160;Xil_Out32(<a class="el" href="xilskey__epshw_8h.html#a7a4932f081f5ec96c124539decda878e">XSK_EFUSEPS_WR_UNLOCK_REG</a>,0xDF0D)</td>
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<p>This macro is used to unlock the efuse controller. </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#gaf4b1541decb6c6f85a71e95c6023e601">XilSKey_EfusePs_Read()</a>, <a class="el" href="group__xilskey__zynq__efuse.html#gae3fb5ac72380a5efddd99df27fde3c41">XilSKey_EfusePs_ReadStatus()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_ENABLE_PROGRAMMING&#160;&#160;&#160;(0x1)</td>
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<p>&lt; EFUSE operation modes and definitions </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a445869d8f60f01261334c1022c4b08f5">XilSKey_EfusePs_ControllerSetReadWriteEnable()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_HAMMING_LOOPS&#160;&#160;&#160;(10)</td>
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<p>&lt; Hamming loops, data and length </p>

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          <td class="memname">#define XSK_EFUSEPS_PGM_STBW_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a4e53a41436c197bcd64236ef178da2c8">XSK_EFUSEPS_PGM_STBW_REG_OFFSET</a>)</td>
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<p>PGM_STBW eFuse program strobe width register. </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>.</p>

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<a class="anchor" id="a4e53a41436c197bcd64236ef178da2c8"></a>
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          <td class="memname">#define XSK_EFUSEPS_PGM_STBW_REG_OFFSET&#160;&#160;&#160;(0x18)</td>
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<p>PGM_STBW eFuse program strobe width register offset. </p>

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          <td class="memname">#define XSK_EFUSEPS_PRGM_STROBE_WIDTH</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RefClk</td><td>)</td>
          <td>&#160;&#160;&#160;((12 * (RefClk))/1000000)</td>
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<p>Strobe width calculation. </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_RD_STBW_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#afd6144e5e4692602259cb57e4db47148">XSK_EFUSEPS_RD_STBW_REG_OFFSET</a>)</td>
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<p>RD_STBW eFuse read strobe width register. </p>
<p>PSS eFUSE register bit defines &amp; description XSK_EFUSEPS_WR_LOCK_STATUS_REG (Write Protection Status Register) </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_RD_STBW_REG_OFFSET&#160;&#160;&#160;(0x1C)</td>
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<p>RD_STBW eFuse read strobe width register offset. </p>

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          <td class="memname">#define XSK_EFUSEPS_RD_STROBE_WIDTH</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RefClk</td><td>)</td>
          <td>&#160;&#160;&#160;((15 * (RefClk))/100000000)</td>
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<p>Modified to have max of 32 bit value. </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_READ_MODE_NORMAL&#160;&#160;&#160;(0x1)</td>
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<p>&lt; ReadModes and definitions </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#gaf4b1541decb6c6f85a71e95c6023e601">XilSKey_EfusePs_Read()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_REFCLK_LOW_FREQ&#160;&#160;&#160;(20000000)</td>
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<p>&lt; EFUSE Reference Clock frequency definitions </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_RSA_HASH_LEN_ECC_CALC&#160;&#160;&#160;(260)</td>
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<p>Rsa Key hash length calculation. </p>

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<p>Rsa Key hash length in bits. </p>

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          <td class="memname">#define XSK_EFUSEPS_SINGLE_MODE&#160;&#160;&#160;(0x0)</td>
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<p>&lt; Mode types and definitions </p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a86aa3b42b03a38e86ae622b0338523cc">XilSKey_EfusePs_ControllerConfig()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_BISR_BLANK&#160;&#160;&#160;(0x00100000)</td>
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<p>eFuse box is blank, i.e., not yet been written to, if set </p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_BISR_DONE&#160;&#160;&#160;(0x80000000)</td>
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<p>Status Register containing BISR Controller status, trim value, and security debug info. </p>
<p>Build in self test finished at boot time </p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_BISR_GO&#160;&#160;&#160;(0x40000000)</td>
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<p>Build in self test finished successfully. </p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a161ad724298fc7d9827bd98c565954fc">XSK_EFUSEPS_STATUS_REG_OFFSET</a>)</td>
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<p>STATUS Status register. </p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#gae3fb5ac72380a5efddd99df27fde3c41">XilSKey_EfusePs_ReadStatus()</a>.</p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_REG_OFFSET&#160;&#160;&#160;(0x10)</td>
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<p>STATUS Status register offset. </p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_SDEBUG_DIS&#160;&#160;&#160;(0x00010000)</td>
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<p>Security debug status, with authentication 0 security debug enabled 1 security debug disabled. </p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_TRIM&#160;&#160;&#160;(0x000000FC)</td>
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<p>Analog trim value. </p>

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          <td class="memname">#define XSK_EFUSEPS_STATUS_WR_PROTECT&#160;&#160;&#160;(0x00003000)</td>
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<p>eFuse write protection, if either bit is set, writes to the eFuse box are disabled </p>

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<a class="anchor" id="a1444e3f0e61dc50eac55f2265d75f208"></a>
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          <td class="memname">#define XSK_EFUSEPS_WR_LOCK_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#af407b20b4194d9c078658ae97e4823a6">XSK_EFUSEPS_WR_LOCK_REG_OFFSET</a>)</td>
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<p>WR_LOCK Write 0x767B to disallow write. </p>

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<a class="anchor" id="af407b20b4194d9c078658ae97e4823a6"></a>
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          <td class="memname">#define XSK_EFUSEPS_WR_LOCK_REG_OFFSET&#160;&#160;&#160;(0x0)</td>
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<p>WR_LOCK Write lock offset. </p>

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<a class="anchor" id="a534303385585d8e6e3473ec38290046c"></a>
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          <td class="memname">#define XSK_EFUSEPS_WR_LOCK_STATUS_BIT&#160;&#160;&#160;(0x1)</td>
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<p>Current state of write protection mode of eFuse subsystem:- 0 Region is writable 1 Region is not writable. </p>
<p>Any attempted writes are ignored, but reads will complete as normal.XSK_EFUSEPS_CONFIG_REG (Configuration Register) </p>

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          <td class="memname">#define XSK_EFUSEPS_WR_LOCK_STATUS_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#ad97de6a7f673891f7e562e76ec4df13c">XSK_EFUSEPS_WR_LOCK_STATUS_REG_OFFSET</a>)</td>
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<p>WR_LOCKSTA Write protection status. </p>

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<p>WR_LOCKSTA Write protection status offset. </p>

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          <td class="memname">#define XSK_EFUSEPS_WR_UNLOCK_REG&#160;&#160;&#160;(<a class="el" href="xilskey__epshw_8h.html#a83ebe761588d9b8b10860833cb746a6d">XSK_EFUSEPS_BASE_ADDRESS</a> + <a class="el" href="xilskey__epshw_8h.html#a6974adcd348488808f7aa8fccaeb9533">XSK_EFUSEPS_WR_UNLOCK_REG_OFFSET</a>)</td>
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<p>WR_UNLOCK Write 0xDF0D to allow write. </p>

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<p>WR_UNLOCK Write 0xDF0D to allow write offset. </p>

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<h2 class="groupheader">Function Documentation</h2>
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          <td class="memname">u32 XilSKey_EfusePs_ControllerConfig </td>
          <td>(</td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>CtrlMode</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>RefClk</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8&#160;</td>
          <td class="paramname"><em>ReadMode</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>This function is used to set the controller mode, read mode along with the read and program strobe width values based on the reference clock. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">CtrlMode</td><td>is the mode of the controller<ul>
<li>XSK_EFUSEPS_REDUNDANCY_MODE</li>
<li>XSK_EFUSEPS_SINGLE_MODE</li>
</ul>
</td></tr>
    <tr><td class="paramname">RefClk</td><td>is the CPU 1x reference clock frequency. Clock frequency can be between 20MHz to 100MHz specified in Hz</td></tr>
    <tr><td class="paramname">ReadMode</td><td>is the read mode of the controller<ul>
<li>XSK_EFUSEPS_READ_MODE_NORMAL</li>
<li>XSK_EFUSEPS_READ_MODE_MARGIN_1</li>
<li>XSK_EFUSEPS_READ_MODE_MARGIN_2</li>
</ul>
</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS no errors occurred.</li>
</ul>
</dd></dl>
<ul>
<li>an error when controller mode is not supported</li>
<li>an error when reference clock is not supported</li>
<li>an error when read mode is not supported</li>
</ul>
<p>Test Cases: Check single mode in CFG Reg Check redundancy mode in CFG Reg Check strobe width values for write mode Check strobe width values for various read mode Check Normal Read mode setting in CFG Reg Check Margin 1 Read mode setting in CFG Reg Check Margin 2 Read mode setting in CFG Reg Boundary Conditions </p>
<p>Check the parameters Mode can be Single or Redundancy mode</p>
<p>Ref Clock should be between 20MHz - 60MHz</p>
<p>3 read modes are supported</p>
<p>Set the controller mode</p>
<p>Set the controller read mode</p>
<p>Program the Strobe width values for read and write 12us is required for write and 150ns is required for read PGM_STBW = ceiling(12us/ref_clk period) RD_STBW = ceiling(150ns/ref_clk period)</p>

<p>References <a class="el" href="xilskey__epshw_8h.html#a181241481bae878db9c1b8bc45eebd3d">XSK_EFUSEPS_CONFIG_REG</a>, <a class="el" href="xilskey__epshw_8h.html#ad585dc497a89d100b768fd0890aa2101">XSK_EFUSEPS_CONFIG_TSU_H_A</a>, <a class="el" href="group__xilskey__psefuse__error__codes.html#gga35d67e0a9db73e1fa64262f5eb8f9d6aa12fc3f5163ee9e27300002aba72c317e">XSK_EFUSEPS_ERROR_CONTROLLER_MODE</a>, <a class="el" href="group__xilskey__psefuse__error__codes.html#gga35d67e0a9db73e1fa64262f5eb8f9d6aa275d0d46da578a5f1e11e78fd31fcbc1">XSK_EFUSEPS_ERROR_READ_MODE</a>, <a class="el" href="group__xilskey__psefuse__error__codes.html#gga35d67e0a9db73e1fa64262f5eb8f9d6aaa657a41e407f120d32c5a4c92337c0d1">XSK_EFUSEPS_ERROR_REF_CLOCK</a>, <a class="el" href="xilskey__epshw_8h.html#a4d7fe5bd7667d9a57c238328f343d95c">XSK_EFUSEPS_PGM_STBW_REG</a>, <a class="el" href="xilskey__epshw_8h.html#a28a3e32054644f36176a139ba4fff520">XSK_EFUSEPS_PRGM_STROBE_WIDTH</a>, <a class="el" href="xilskey__epshw_8h.html#a9383ce46dbabb7c855569ef88ed73dc6">XSK_EFUSEPS_RD_STBW_REG</a>, <a class="el" href="xilskey__epshw_8h.html#a576c8c9ba3aa6a1246f498bc9f6ed60c">XSK_EFUSEPS_RD_STROBE_WIDTH</a>, <a class="el" href="xilskey__epshw_8h.html#a1926299738dd5272aaddea96259bffb0">XSK_EFUSEPS_REFCLK_LOW_FREQ</a>, and <a class="el" href="xilskey__epshw_8h.html#ab89168a190f2b176fc52aa119fbfd4bb">XSK_EFUSEPS_SINGLE_MODE</a>.</p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#gaf4b1541decb6c6f85a71e95c6023e601">XilSKey_EfusePs_Read()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">void XilSKey_EfusePs_ControllerSetReadWriteEnable </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>ReadWriteEnable</em></td><td>)</td>
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<p>This function is used to enable the read/write/program the eFUSE array. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">ReadWriteEnable</td><td>0x1 - Enable programming 0x2 - Enable read 0x4 - Enable write </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd></dd></dl>
<p>Test Cases </p>
<p>Reset the values Disable programming Disable reading Disable writing</p>

<p>References <a class="el" href="xilskey__epshw_8h.html#a1c34f551c39236943d36103cb150353b">XSK_EFUSEPS_CONTROL_PS_EN</a>, <a class="el" href="xilskey__epshw_8h.html#a634af4b7edb7109523e14d841c4ac283">XSK_EFUSEPS_CONTROL_RD_DIS</a>, <a class="el" href="xilskey__epshw_8h.html#a37aa46e53d68f6c77c5e3d6f9a6943aa">XSK_EFUSEPS_CONTROL_REG</a>, <a class="el" href="xilskey__epshw_8h.html#a9c6d0eb879aee49e3109cba85d60a5ff">XSK_EFUSEPS_CONTROL_WR_DIS</a>, and <a class="el" href="xilskey__epshw_8h.html#a8b6db89bcacd73a511cfc74cd117d058">XSK_EFUSEPS_ENABLE_PROGRAMMING</a>.</p>

<p>Referenced by <a class="el" href="group__xilskey__zynq__efuse.html#gaf4b1541decb6c6f85a71e95c6023e601">XilSKey_EfusePs_Read()</a>, and <a class="el" href="group__xilskey__zynq__efuse.html#ga63c6c25524196e392935e0c9c9e34825">XilSKey_EfusePs_Write()</a>.</p>

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          <td class="memname">u8 XilSKey_EfusePs_EccDecode </td>
          <td>(</td>
          <td class="paramtype">const u8 *&#160;</td>
          <td class="paramname"><em>Corrupt</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Syndrome</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>This function is used to decode the incoming encoded byte. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Corrupt</td><td>is the input encoded data. It has 26 bit data with 5 bit parity data</td></tr>
    <tr><td class="paramname">Syndrome</td><td>is the output updated with the parity error information.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>position of the error in the data byte</dd></dl>
<p>TDD Cases: Check the parameters Check the decode with out any error Check the decode with 1 bit error Check the decode with 2 bit error Check the decode for boundary cases Check for memory corruption </p>

<p>References <a class="el" href="xilskey__eps_8c.html#a7f051e409a483c56b42c3112c53f2b46">ErrorCodeIndex</a>, and <a class="el" href="xilskey__eps_8c.html#ae2b9f8f3a34a450d90b88bb79b29801f">Matrix</a>.</p>

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          <td class="memname">void XilSKey_EfusePs_EccEncode </td>
          <td>(</td>
          <td class="paramtype">const u8 *&#160;</td>
          <td class="paramname"><em>InData</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Ecc</em>&#160;</td>
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<p>This function is used to encode the incoming data byte. </p>
<p>It uses hamming (31,26) algorithm. 26 bits are encoded to 31 bits</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InData</td><td>is 26 bit input data with each bit represented in one byte</td></tr>
    <tr><td class="paramname">Ecc</td><td>is the 31 bit encoded data with each bit represented in one byte</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<p>TDD Cases: Check the parameters Check the encoded data for different input data Check the input data for boundary cases Check for memory corruption </p>

<p>References <a class="el" href="xilskey__eps_8c.html#ae2b9f8f3a34a450d90b88bb79b29801f">Matrix</a>.</p>

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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
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<p>This function is used to generate the matrix map of the G and H for hamming code (31,26). </p>
<p>G is [31,5] and defined as [A|I], I is identity matrix of [5,5].</p>
<dl class="section return"><dt>Returns</dt><dd>None</dd></dl>
<p>TDD Cases: Check the generated matrix Check the memory corruption of the generated matrix </p>

<p>References <a class="el" href="xilskey__eps_8c.html#a7f051e409a483c56b42c3112c53f2b46">ErrorCodeIndex</a>, and <a class="el" href="xilskey__eps_8c.html#ae2b9f8f3a34a450d90b88bb79b29801f">Matrix</a>.</p>

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          <td class="memname">u8 XilSKey_EfusePs_IsAddressXilRestricted </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Addr</em></td><td>)</td>
          <td></td>
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<p>This function is used to check whether eFuse bit is xilinx reserved bit or not. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Addr</td><td>is the address of the eFuse bit.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS if address corresponds to restricted eFuse bit.</li>
</ul>
</dd></dl>
<ul>
<li>XST_FAILURE is address corresponds to non-restricted eFuse bit.</li>
</ul>
<p>Test Cases: with different address values Boundary values for addr </p>
<p>Check for xilinx test bits</p>
<p>Check for xilinx reserved bits</p>

<p>References <a class="el" href="xilskey__epshw_8h.html#ad902de733258e3dee29cba902a315d40">XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR</a>, <a class="el" href="xilskey__epshw_8h.html#ac226f4af9d59902bb9415a7f38992090">XSK_EFUSEPS_APB_TRIM_BITS_START_ADDR_2ND_HALF</a>, <a class="el" href="xilskey__epshw_8h.html#a81347f7506085d433d18c529b7f8d6e6">XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x20</a>, and <a class="el" href="xilskey__epshw_8h.html#a30a30145d45855d1976ec41ef8d3a664">XSK_EFUSEPS_APB_XILINX_RSVD_TEST_BIT_x23F</a>.</p>

<p>Referenced by <a class="el" href="xilskey__epshw_8h.html#a35d72d812bd2eedfe0fe1cf855819774">XilSKey_EfusePs_ReadEfuseBit()</a>, and <a class="el" href="xilskey__epshw_8h.html#a2c6ad78fcde90b22766572624ce2f236">XilSKey_EfusePs_WriteEfuseBit()</a>.</p>

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          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">u8 *&#160;</td>
          <td class="paramname"><em>Data</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>This function is used to read the eFuse bit value. </p>
<p>Before using this function set the controller mode and read mode as required. Also, strobe width values are to be set properly based on the reference clock for successful reading</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Addr</td><td>is the address of the eFuse bit.</td></tr>
    <tr><td class="paramname">Data</td><td>has the read eFuse value stored in it.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS for successfully reading the value.</li>
</ul>
</dd></dl>
<ul>
<li>an error when addr is restricted</li>
</ul>
<p>Test Cases Read in Single mode Read in redundancy mode Read for restricted address Boundary Checks for address </p>

<p>References <a class="el" href="xilskey__eps_8c.html#aa96506a89bc84dd4db81ce860cd63ef0">XilSKey_EfusePs_IsAddressXilRestricted()</a>, and <a class="el" href="group__xilskey__psefuse__error__codes.html#gga35d67e0a9db73e1fa64262f5eb8f9d6aad0082f74347e4ad447374d6992e82e55">XSK_EFUSEPS_ERROR_ADDRESS_XIL_RESTRICTED</a>.</p>

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          <td class="memname">u32 XilSKey_EfusePs_WriteEfuseBit </td>
          <td>(</td>
          <td class="paramtype">u32&#160;</td>
          <td class="paramname"><em>Addr</em></td><td>)</td>
          <td></td>
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<p>This function is used to program the eFuse bit value. </p>
<p>Before using this function set the controller mode and read mode as required. Also, strobe width values are to be set properly based on the reference clock for successful programming</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Addr</td><td>is the address of the eFuse bit.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><ul>
<li>XST_SUCCESS after successful writing.</li>
</ul>
</dd></dl>
<ul>
<li>an error when addr is restricted</li>
</ul>
<p>Test Cases Write in Single mode Write in redundancy mode Write for restricted address Boundary Checks for address Strobe width are not proper (Check if it makes sense) </p>
<p>Check if Address is restricted</p>
<p>Send success when bit is already programmed</p>
<p>Providing 15us delay Timer takes 100ns as slice. 15us = 150 * 100ns</p>

<p>References <a class="el" href="xilskey__utils_8c.html#a2a71bd701b24852c007d5ebad8acc257">XilSKey_Efuse_IsTimerExpired()</a>, <a class="el" href="xilskey__utils_8c.html#ab2eaa24ca4b7d40aab0d75804d217616">XilSKey_Efuse_SetTimeOut()</a>, <a class="el" href="xilskey__eps_8c.html#aa96506a89bc84dd4db81ce860cd63ef0">XilSKey_EfusePs_IsAddressXilRestricted()</a>, and <a class="el" href="group__xilskey__psefuse__error__codes.html#gga35d67e0a9db73e1fa64262f5eb8f9d6aad0082f74347e4ad447374d6992e82e55">XSK_EFUSEPS_ERROR_ADDRESS_XIL_RESTRICTED</a>.</p>

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